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? e94108-te sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. description the ILX511 is a rectangular reduction type ccd linear image sensor designed for bar code pos hand scanner and optical measuring equipment use. a built-in timing generator and clock-drivers ensure single 5 v power supply for easy use. features number of effective pixels: 2048 pixels pixel size: 14 ? 200 ? (14 ? pitch) single 5 v power supply ultra-high sensitivity built-in timing generator and clock-drivers built-in sample-and-hold circuit maximum clock frequency: 2mhz absolute maximum ratings supply voltage v dd 6v operating temperature ?0 to +60 ? storage temperature ?0 to +80 ? 2048-pixel ccd linear image sensor (b/w) 22 pin dip (plastic) pin configuration (top view) ILX511 22 21 20 19 18 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11 2048 1 v dd v dd v dd gnd v gg gnd gnd v dd nc nc gnd f rog nc v dd nc nc v dd f clk shsw gnd gnd v out block diagram 22 21 20 19 18 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 readout gate v dd v dd shsw v gg gnd gnd v dd nc nc gnd nc v dd nc nc v dd f clk gnd gnd gnd v out ccd analog shift register a a clock-drivers clock plse generator/ sample-and-hold pulse generator mode selector readout gate pulse generator 11 f rog internal structure output amplifier s/h circuit v dd d13 d14 d32 s1 s2 s3 s2046 s2047 s2048 d33 d34 d35 d36 d37 d38
? ILX511 pin description mode description recommended voltage input clock voltage condition (note) note) this is applied to the all pulses applied externally. ( f clk, f rog) pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 symbol v out gnd gnd shsw f clk v dd nc nc v dd nc f rog gnd nc nc v dd gnd gnd v gg gnd v dd v dd v dd description signal output gnd gnd switch (with s/h or without s/h) clock pulse input 5v power supply nc nc 5v power supply nc readout gate pulse input gnd nc nc 5v power supply gnd gnd output circuit gate bias gnd 5v power supply 5v power supply 5v power supply mode in use pin 4 (shsw) with s/h gnd without s/h v dd item min. typ. max. unit v dd 4.5 5.0 5.5 v item min. typ. max. unit v ih 4.5 5.0 5.5 v v il 0 0.5 v item symbol min. typ. max. unit input capacity of f clk pin c f clk ?0 pf
? ILX511 electro-optical characteristics (ta = 25 ?, v dd = 5 v, clock frequency: 1 mhz, light source = 3200 k, ir cut filter: cm-500s (t = 1.0 mm), without s/h mode) note) 1. for the sensitivity test light is applied with a uniform intensity of illumination. 2. light source: led l = 660nm 3. prnu is defined as indicated below. ray incidence conditions are the same as for note 1. prnu = (v max -v min )/2 100 (%) v ave the maximum output of all the valid pixels is set to v max , the minimum output to v min and the average output to v ave . 4. integration time is 10ms. 5. typical value is used for clock pulse and readout pulse. v out = 500 mv. 6. dr = v sat /v drk . when optical integration time is shorter, the dynamic range sets wider because dark voltage is in proportion to optical integration time. 7. se = v sat /r1 8. vos is defined as indicated below. item symbol min. typ. max. unit remarks sensitivity 1 sensitivity 2 sensitivity nonuniformity saturation output voltage dark voltage average dark signal nonuniformity image lag dynamic range saturation exposure 5 v current consumption total transfer efficiency output impedance offset level r1 150 200 250 v/(lx ?s) r2 1800 v/(lx ?s) prnu 5.0 10.0 % v sat 0.6 0.8 v v drk 3.0 6.0 mv dsnu 6.0 12.0 mv il 1 % dr 267 se 0.004 lx ?s i vdd 5.0 10.0 ma tte 92.0 98.0 % z o 250 v os 2.8 v note 1 note 2 note 3 note 4 note 4 note 5 note 6 note 7 note 8 aaaa aaaa aaa gnd vos v out d30 d31 d32 s1
? ILX511 clock timing diagram (without s/h mode) 2088 or more clock pulses are required. f rog f clk v out 5 0 2086 5 0 d1 d2 d3 d4 d5 d10 d11 d12 d13 d14 d31 d32 s1 s2 s3 d30 s4 s2045 s2046 s2047 s2048 d33 d34 d35 d36 d37 d38 optical black (18 pixels) dummy signal (32 pixels) effective picture elements signal (2048 pixels) dummy signal (6 pixels) 1-line output period (2086 pixels) 1 3 2 1 * * without s/h mode (4pin v dd )
? ILX511 clock timing diagram (with s/h mode) 2088 or more clock pulses are required. f rog f clk v out 5 0 2086 5 0 d0 d1 d2 d3 d4 d5 d9 d10 d11 d12 d13 d31 d32 s1 s2 s3 d30 s4 s2045 s2046 s2047 s2048 d33 d34 d35 d36 d37 d38 optical black (18 pixels) dummy signal (33 pixels) effective picture elements signal (2048 pixels) dummy signal (6 pixels) 1-line output period (2087 pixels) 1 0 1 2 3
? ILX511 f clk timing (for all modes) note 1) 100 t4 / (t3 + t4) f rog, f clk timing f rog f clk t5 t6 t7 t8 t9 item f rog, f clk pulse timing 1 f rog, f clk pulse timing 2 f rog pulse rise/fall time f rog pulse period symbol min. typ. max. unit t5 0 3000 t9 1000 3000 ns t6, t8 0 10 t7 3000 5000 item f clk pulse rise/fall time f clk pulse duty (note 1) symbol min. typ. max. unit t1, t2 0 10 100 ns 405060 % f clk t1 t2 t4 t3
? ILX511 f clk, vout timing (note 1) note 1) fck = 1mhz, f clk pulse duty = 50 %, f clk pulse rise/fall time = 10 ns note 2) output waveform when internal s/h is in use. note 3) indicates the correspondence of clock pulse and data period. t10 t11 vout vout (note 2) t12 * aaaa aaaa aaaa aaaa f clk (note 3) item f clk-vout 1 f clk-vout 2 f clk-vout * (with s/h) symbol min. typ. max. unit t10 40 115 280 t11 55 120 205 ns t12 10 165 240
? ILX511 wavelength (nm) relative sensitivity 0 0.2 0.4 0.6 0.8 1.0 400 500 600 700 800 900 1000 spectral sensitivity (typ.) (ta = 25?) normalized spatial frequency t =560nm h?tf 0 0.2 0.4 0.6 0.8 1.0 0 0.2 0.4 0.6 0.8 1 spatial frequency (cycles/mm) 0 7.1 14.3 21.4 28.6 35.7 mtf of main scanning direction (typ.) ta?mbient temperature (?) dark voltage rate 0.10 1.00 10.0 0 102030 405060 dark voltage rate vs. ambient temperature (typ.)
? ILX511 5 t int?ntegration time (ms) output voltag rate 0.1 1 11050 output voltage rate vs. integration time (typ.) clock frequency (mhz) current consumption rate 0 0.5 1.0 1.5 2.0 0 0.5 1.0 1.5 2.0 current consumption rate vs. clock frequency (typ.) v dd (v) 2.4 2.6 2.8 3.0 3.2 4.5 4.75 5 5.25 5.5 offset level vs. v dd (typ.) ta?mbient temperature (?) v os ?ffset level (v) 2.4 2.6 2.8 3.0 3.2 0204060 offset level vs. ambient temperature (typ.) v os ?ffset level (v)
?0 ILX511 application circuit (without s/h mode (note)) note) this circuit diagram is the case when internal s/h is not used. frog f rog f clk 0.01 22/10v output signal 2sa1175 3k w 10/16v 5v nc v dd nc nc v dd fclk shsw gnd gnd v out gnd nc nc v dd gnd gnd v gg gnd v dd v dd v dd + + 22 21 20 19 18 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party and other right due to same.
?1 ILX511 notes on handling 1) static charge prevention ccd image sensors are easily damaged by static discharge. before handling, be sure to take the following protective measures. a) either handle bare handed or use non-chargeable gloves, clothes or material. also use conductive shoes. b) when handling directly use an earth band. c) install a conductive mat on the floor or working table to prevent the generation of static electricity. d) ionized air is recommended for discharge when handling ccd image sensors. e) for the shipment of mounted substrates use cartons treated for the prevention of static charges. 2) notes on handling ccd cer-dip package the following points should be observed when handling and installing this package. a) (1) compressive strength: 39n/surface (do not apply any load more than 0.7 mm inside the outer perimeter of the glass portion.) (2) shearing strength: 29n/surface (3) tensile strength: 29n/surface (4) torsional strength: 0.9nm b) in addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. c) be aware that any of the following can cause the glass to crack because the upper and lower ceramic layers are shielded by low-melting glass. (1) applying repetitive bending stress to the external leads. (2) applying heat to the external leads for an extended period of time with a soldering iron. (3) rapid cooling or heating. (4) applying a load or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) prying the upper or lower ceramic layers away at a support point of the low-melting glass. note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. 3) soldering a) make sure the package temperature does not exceed 80 ?. b) solder dipping in a mounting furnace causes damage to the glass and other defects. use a grounded 30w soldering iron and solder each pin in less than 2 seconds. for repairs and remount, cool sufficiently. c) to dismount image sensors, do not use a solder suction equipment. when using an electric desoldering tool, ground the controller. for the control system, use a zero cross type. upper ceramic layer lower ceramic layer low-melting glass 39n (1) (4) (3) (2) 29n 29n 0.9nm
?2 ILX511 4) dust and dirt protection a) operate in clean environments. b) do not either touch glass plates by hand or have any object come in contact with glass surfaces. should dirt stick to a glass surface blow it off with an air blower. (for dirt stuck through static electricity, ionized air is recommended.) c) clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. be careful not to scratch the glass. d) keep in case to protect from dust and dirt. to prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) exposure to high temperature or humidity will affect the characteristics. accordingly avoid storage or usage in such conditions. 6) ccd image sensors are precise optical equipment that should not be subject to mechanical shocks. 7) make sure the input pulse should not be -1 v or below. 8) normal output signal is not obtained immediately after device switch on. use the output signal added 22500 pulses or above to f clk clock pulse.
package structure v h 6.46 0.8 22 28.672 (14m 2048pixels) 41.6 0.5 1 11 12 no.1 pixel 40.2 5.0 0.5 4.0 0.5 2.54 0.51 3.65 4.45 0.5 0.25 0?to 9 10.16 10.0 0.5 9.0 0.3 1. the height from the bottom to the sensor surface is 2.45 0.3mm. 2. the thickness of the cover glass is 0.8mm, and the refractive index is 1.5. 22pin dip (400mil) (at stand off) m package material lead treatment lead material package weight cer-dip tin plating 42 alloy 5.2g package outline unit : mm ILX511 ?3

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